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This commit is contained in:
Robin Bärtschi 2025-03-14 06:27:09 +01:00
parent e5f576251a
commit 13da26acdb
1 changed files with 12 additions and 0 deletions
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12
asm/amd64/codegen.go
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@ -366,6 +366,8 @@ func fixupInstruction(i Instruction) []Instruction {
if lhs, ok := i.Lhs.(Stack); ok { if lhs, ok := i.Lhs.(Stack); ok {
if rhs, ok := i.Rhs.(Stack); ok { if rhs, ok := i.Rhs.(Stack); ok {
return []Instruction{ return []Instruction{
comment("FIXUP: Stack and Stack for Mov"),
comment(i.InstructionString()),
&SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: rhs}, &SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: rhs},
&SimpleInstruction{Opcode: Mov, Lhs: lhs, Rhs: Register(R10)}, &SimpleInstruction{Opcode: Mov, Lhs: lhs, Rhs: Register(R10)},
} }
@ -374,6 +376,8 @@ func fixupInstruction(i Instruction) []Instruction {
case Imul: case Imul:
if lhs, ok := i.Lhs.(Stack); ok { if lhs, ok := i.Lhs.(Stack); ok {
return []Instruction{ return []Instruction{
comment("FIXUP: Stack as Dst for Imul"),
comment(i.InstructionString()),
&SimpleInstruction{Opcode: Mov, Lhs: Register(R11), Rhs: lhs}, &SimpleInstruction{Opcode: Mov, Lhs: Register(R11), Rhs: lhs},
&SimpleInstruction{Opcode: Imul, Lhs: Register(R11), Rhs: i.Rhs}, &SimpleInstruction{Opcode: Imul, Lhs: Register(R11), Rhs: i.Rhs},
&SimpleInstruction{Opcode: Mov, Lhs: lhs, Rhs: Register(R11)}, &SimpleInstruction{Opcode: Mov, Lhs: lhs, Rhs: Register(R11)},
@ -384,12 +388,16 @@ func fixupInstruction(i Instruction) []Instruction {
if lhs, ok := i.Lhs.(Stack); ok { if lhs, ok := i.Lhs.(Stack); ok {
if rhs, ok := i.Rhs.(Stack); ok { if rhs, ok := i.Rhs.(Stack); ok {
return []Instruction{ return []Instruction{
comment("FIXUP: Stack and Stack for Binary"),
comment(i.InstructionString()),
&SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: rhs}, &SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: rhs},
&SimpleInstruction{Opcode: i.Opcode, Lhs: lhs, Rhs: Register(R10)}, &SimpleInstruction{Opcode: i.Opcode, Lhs: lhs, Rhs: Register(R10)},
} }
} }
} else if lhs, ok := i.Lhs.(Imm); ok && i.Opcode == Idiv { } else if lhs, ok := i.Lhs.(Imm); ok && i.Opcode == Idiv {
return []Instruction{ return []Instruction{
comment("FIXUP: Imm as Dst for Idiv"),
comment(i.InstructionString()),
&SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: lhs}, &SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: lhs},
&SimpleInstruction{Opcode: Idiv, Lhs: Register(R10)}, &SimpleInstruction{Opcode: Idiv, Lhs: Register(R10)},
} }
@ -398,12 +406,16 @@ func fixupInstruction(i Instruction) []Instruction {
if lhs, ok := i.Lhs.(Stack); ok { if lhs, ok := i.Lhs.(Stack); ok {
if rhs, ok := i.Rhs.(Stack); ok { if rhs, ok := i.Rhs.(Stack); ok {
return []Instruction{ return []Instruction{
comment("FIXUP: Stack and Stack for Cmp"),
comment(i.InstructionString()),
&SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: rhs}, &SimpleInstruction{Opcode: Mov, Lhs: Register(R10), Rhs: rhs},
&SimpleInstruction{Opcode: i.Opcode, Lhs: lhs, Rhs: Register(R10)}, &SimpleInstruction{Opcode: i.Opcode, Lhs: lhs, Rhs: Register(R10)},
} }
} }
} else if lhs, ok := i.Lhs.(Imm); ok { } else if lhs, ok := i.Lhs.(Imm); ok {
return []Instruction{ return []Instruction{
comment("FIXUP: Imm Dst for Cmp"),
comment(i.InstructionString()),
&SimpleInstruction{ &SimpleInstruction{
Opcode: Mov, Opcode: Mov,
Lhs: Register(R11), Lhs: Register(R11),